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Z8F082ASH020SC Datasheet(PDF) 197 Page - Zilog, Inc.

Part # Z8F082ASH020SC
Description  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8F082ASH020SC Datasheet(HTML) 197 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F08xA Series
Product Specification
179
AND dst, src
dst
← dst AND src
r
r
52
–
*
*
0
–
–
2
3
rIr
53
2
4
RR
54
3
3
RIR
55
3
4
RIM
56
3
3
IR
IM
57
3
4
ANDX dst, src
dst
← dst AND src
ER
ER
58
–
*
*
0
–
–
4
3
ER
IM
59
4
3
ATM
Block all interrupt and
DMA requests during
execution of the next 3
instructions
2F
–
–––
–
–
1
2
BCLR bit, dst
dst[bit]
← 0r
E2
–
*
*
0
–
–
2
2
BIT p, bit, dst
dst[bit]
← pr
E2
–
*
*
0
–
–
2
2
BRK
Debugger Break
00
–
–
–
–
–
–
1
1
BSET bit, dst
dst[bit]
← 1r
E2
–
*
*
0
–
–
2
2
BSWAP dst
dst[7:0]
← dst[0:7]
R
D5
X
*
*
0
–
–
2
2
BTJ p, bit, src, dst
if src[bit] = p
PC
← PC + X
r
F6
–
–––
–
–
3
3
Ir
F7
3
4
BTJNZ bit, src, dst if src[bit] = 1
PC
← PC + X
r
F6
–
–––
–
–
3
3
Ir
F7
3
4
BTJZ bit, src, dst
if src[bit] = 0
PC
← PC + X
r
F6
–
–––
–
–
3
3
Ir
F7
3
4
CALL dst
SP
← SP -2
@SP
← PC
PC
← dst
IRR
D4
–
–––
–
–
2
6
DA
D6
3
3
CCF
C
← ~C
EF
*
–––
–
–-
1
2
CLR dst
dst
← 00H
R
B0
–
–
–
–
–
–
2
2
IR
B1
2
3
Table 116. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
Symbolic Operation
Address Mode
Opcode(s)
(Hex)
Flags
Fetch
Cycles
Instr.
Cycles
dst
src
C
Z
S
V
D
H
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1



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