Z8F082ASH020SC datasheet(55/244 Pages) ZILOG

55 / 244 page

PS024705-0405

P R E L I M I N A R Y

General-Purpose I/O

Z8 Encore! XP® F08xA Series

Product Specification

GPIO Control Register Definitions

Four registers for each Port provide access to GPIO control, input data, and output data.

Table 15 lists these Port registers. Use the Port A–D Address and Control registers

together to provide access to sub-registers for Port configuration and control.

Port A–D Address Registers

The Port A–D Address registers select the GPIO Port functionality accessible through the

Port A–D Control registers. The Port A–D Address and Control registers combine to pro-

vide access to all GPIO Port controls (Table 16).

Table 15. GPIO Port Registers and Sub-Registers

Port Register Mnemonic

Port Register Name

PxADDR

Port A–D Address Register

(Selects sub-registers)

PxCTL

Port A–D Control Register

(Provides access to sub-registers)

PxIN

Port A–D Input Data Register

PxOUT

Port A–D Output Data Register

Port Sub-Register Mnemonic

Port Register Name

PxDD

Data Direction

PxAF

Alternate Function

PxOC

Output Control (Open-Drain)

PxHDE

High Drive Enable

PxSMRE

STOP Mode Recovery Source Enable

PxPUE

Pull-up Enable

PxAFS1

Alternate Function Set 1

PxAFS2

Alternate Function Set 2

Table 16. Port A–D GPIO Address Registers (PxADDR)

BITS

FIELD

PADDR[7:0]

RESET

00H

R/W

R/WR/W

ADDR

FD0H, FD4H, FD8H, FDCH

Z8F082ASH020SC Datasheet(PDF) 55 Page - Zilog, Inc.

Z8F082ASH020SC Datasheet(HTML) 55 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL