ZLP12840OPTMCU datasheet(44/58 Pages) ZILOG

44 / 58 page

PS024406-0106

P R E L I M I N A R Y

ZLP12840 OTP MCU

Product Specification

Îîëí ÎÐ ã ðð¸

Îð ã Ð±®¬ ð

Îï ã Ð±®¬ ï

Îî ã Ð±®¬ î

Îí ã Ð±®¬ í

But if:

Îîëí ÎÐ ã ðÜ¸

Îð ã ÝÌÎð

Îï ã ÝÌÎï

Îî ã ÝÌÎî

Îí ã ÝÌÎí

The counter/timers are mapped into ERF group D. Access is easily performed using the

following code segment.

ÔÜ ÎÐô ýðÜ¸

å Í»´»½¬ ÛÎÚ Ü º±® ¿½½»-- ¬± Þ¿²µ Ü

å ø©±®µ·²¹ ®»¹·-¬»® ¹®±«° ð÷

ÔÜ Îðôý¨¨

å ´±¿¼ ÝÌÎð

ÔÜ ïô ý¨¨

å ´±¿¼ ÝÌÎï

ÔÜ Îïô î

å ÝÌÎî

ÝÌÎï

ÔÜ ÎÐô ýéÜ¸

å Í»´»½¬ Û¨°¿²¼»¼ Î»¹·-¬»® Þ¿²µ Ü ¿²¼ ©±®µ·²¹

å ®»¹·-¬»® ¹®±«° é ±º Þ¿²µ ð º±® ¿½½»--ò

ÔÜ éï¸ô î

å ÝÌÎî

®»¹·-¬»® éï¸

ÔÜ Îïô î

å ÝÌÎî

®»¹·-¬»® éï¸

Linear Memory Addressing

In addition to using the RP Register to designate a bank and working register group for 8-

bit or 4-bit addressing, programs can use 12-bit linear addressing to load a register in any

other bark to or from a register in the current bank. Linear addressing is implemented in

the LDX and LDXI instructions only. Linear addressing treats the register file as if all of

the registers are logically ordered end-to-end, as opposed to being grouped into banks and

working register groups, as shown in Figure 11 on page 35. For linear addressing, register

file addresses are numbered sequentially from Bank 0, register 00h to Bank 0, register

FFh, then continuing with Bank 1, register 00h, and so on up to Bank F, register FFh.

Using the LDX and/or the LDXI instructions, either the target or destination register loca-

tion can be addressed through a 12-bit linear address value stored in a general-purpose

ZLP12840OPTMCU Datasheet(PDF) 44 Page - Zilog, Inc.

ZLP12840OPTMCU Datasheet(HTML) 44 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL