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ADE9153A Datasheet(PDF) 35 Page - Analog Devices |
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ADE9153A Datasheet(HTML) 35 Page - Analog Devices |
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35 / 50 page  Data Sheet ADE9153A Rev. 0 | Page 35 of 50 Address Name Description Length (Bits) Reset Access 0x4B0 EP_CFG Energy and power accumulation configuration. 16 0x0000 R/W 0x4B1 PWR_TIME Power update time configuration. 16 0x00FF R/W 0x4B2 EGY_TIME Energy accumulation update time configuration. 16 0x00FF R/W 0x4B4 CRC_FORCE This register forces an update of the CRC of configuration registers. 16 0x0000 W 0x4B6 TEMP_CFG Temperature sensor configuration register. 16 0x0000 R/W 0x4B7 TEMP_RSLT Temperature measurement result. 16 0x0000 R 0x4B9 AI_PGAGAIN This register configures the PGA gain for Current Channel A. 16 0x0000 R/W 0x4BF WR_LOCK This register enables the configuration lock feature. 16 0x0000 R/W 0x4C0 MS_STATUS_IRQ The Tier 2 status register for the autocalibration mSure system related interrupts. Any bit set in this register causes the corresponding bit in the status register to be set. This register is cleared on a read and all bits are reset. If a new status bit arrives on the same clock on which the read occurs, the new status bit remains set; in this way, no status bit is missed. 16 0x0000 R 0x4C1 EVENT_STATUS Tier 2 status register for power quality event related interrupts. See the MS_STATUS_IRQ description. 16 0x0000 R 0x4C2 CHIP_STATUS Tier 2 status register for chip error related interrupts. See the MS_STATUS_IRQ description. 16 0x0000 R 0x4DC UART_BAUD_SWITCH This register switches the UART Baud rate between 4800 Baud and 115,200 Baud. Writing a value of 0x0052 sets the Baud rate to 115,200 Baud; any other value maintains a Baud rate of 4800. 16 0x0000 W 0x4FE Version Version of the ADE9153B IC. 16 0x0000 R 0x600 AI_WAV_1 SPI burst read accessible registers organized functionally. See AI_WAV. 32 0x00000000 R 0x601 AV_WAV_1 SPI burst read accessible registers organized functionally. See AV_WAV. 32 0x00000000 R 0x602 BI_WAV_1 SPI burst read accessible registers organized functionally. See BI_WAV. 32 0x00000000 R 0x604 AIRMS_1 SPI burst read accessible registers organized functionally. See AIRMS. 32 0x00000000 R 0x605 BIRMS_1 SPI burst read accessible registers organized functionally. See BIRMS. 32 0x00000000 R 0x606 AVRMS_1 SPI burst read accessible registers organized functionally. See AVRMS. 32 0x00000000 R 0x608 AWATT_1 SPI burst read accessible registers organized functionally. See AWATT. 32 0x00000000 R 0x60A AFVAR_1 SPI burst read accessible registers organized functionally. See AFVAR. 32 0x00000000 R 0x60C AVA_1 SPI burst read accessible registers organized functionally. See AVA. 32 0x00000000 R 0x60E APF_1 SPI burst read accessible registers organized functionally. See APF. 32 0x00000000 R 0x610 AI_WAV_2 SPI burst read accessible registers organized by phase. See AI_WAV. 32 0x00000000 R 0x611 AV_WAV_2 SPI burst read accessible registers organized by phase. See AV_WAV. 32 0x00000000 R 0x612 AIRMS_2 SPI burst read accessible registers organized by phase. See AIRMS. 32 0x00000000 R 0x613 AVRMS_2 SPI burst read accessible registers organized by phase. See AVRMS. 32 0x00000000 R 0x614 AWATT_2 SPI burst read accessible registers organized by phase. See AWATT. 32 0x00000000 R 0x615 AVA_2 SPI burst read accessible registers organized by phase. See AVA. 32 0x00000000 R 0x616 AFVAR_2 SPI burst read accessible registers organized by phase. See AFVAR. 32 0x00000000 R 0x617 APF_2 SPI burst read accessible registers organized by phase. See APF. 32 0x00000000 R 0x618 BI_WAV_2 SPI burst read accessible registers organized by phase. See BI_WAV. 32 0x00000000 R 0x61A BIRMS_2 SPI burst read accessible registers organized by phase. See BIRMS. 32 0x00000000 R |
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