SH7041A datasheet(352/923 Pages) RENESAS

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314

Counter Start

Channel

CST4

Channel 4 (TCNT4)

CST3

Channel 3 (TCNT3)

CST2

Channel 2 (TCNT2)

CST1

Channel 1 (TCNT1)

CST0

Channel 0 (TCNT0)

Bit n: CSTn

Description

TCNTn count is halted (initial value)

TCNTn counts

Note:

n = 4 to 0. However, CST4 is bit 7, CST3 is bit 6.

If 0 is written to the CST bit during operation with the TIOC pin in output status, the counter

stops, but the TIOC pin output compare output level is maintained. If a write is done to the

TIOR register while the CST bit is a 0, the pin output level is updated to the established

initial output value. In complementary PWM mode or reset sync PWM mode, when a 0 is

written to the CST bit of a TIOC pin in output mode during operation, it returns to the initial

output.

• Bits 5–3—Reserved: These bits always read as 0. The write value should always be 0.

12.2.9

Timer Synchro Register (TSYR)

The timer synchro register (TSYR) is an 8-bit read/write register that selects independent or

synchronous TCNT counter operation for channels 0–4. Channels for which 1 is set in the

corresponding bit will be synchronized. TSYR is initialized to H'00 upon power-on reset or

standby mode. Manual reset does not initialize TSYR.

Bit:

SYNC4

SYNC3

—

SYNC2

SYNC1

SYNC0

Initial value:

R/W:

R/W

• Bits 7, 6, 2–0—Timer Synchronization 4–0 (SYNC4–SYNC0): Selects operation independent

of, or synchronized to, other channels. Synchronous operation allows synchronous clears due

to multiple TCNT synchronous presets and other channel counter clears. A minimum of two

channels must have SYNC bits set to 1 for synchronous operation. For synchronization

clearing, it is necessary to set the TCNT counter clear sources (the CCLR2–CCLR0 bits of the

TCR register), in addition to the SYNC bit. The counter start to channel and bit-to-channel

correspondence are indicated in the tables below.

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