Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

SH7041A Datasheet(PDF) 351 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 351 Page - Renesas Technology Corp

Back Button SH7041A Datasheet HTML 347Page - Renesas Technology Corp SH7041A Datasheet HTML 348Page - Renesas Technology Corp SH7041A Datasheet HTML 349Page - Renesas Technology Corp SH7041A Datasheet HTML 350Page - Renesas Technology Corp SH7041A Datasheet HTML 351Page - Renesas Technology Corp SH7041A Datasheet HTML 352Page - Renesas Technology Corp SH7041A Datasheet HTML 353Page - Renesas Technology Corp SH7041A Datasheet HTML 354Page - Renesas Technology Corp SH7041A Datasheet HTML 355Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 351 / 923 page
background image
313
12.2.7
Timer General Register (TGR)
Each timer general register (TGR) is a 16-bit register that can function as either an output compare
register or an input capture register. There are a total of sixteen TGR, four each for channels 0, 3,
and 4, and two each for channels 1 and 2. The TGRC and TGRD of channels 0, 3, and 4 can be set
to operate as buffer registers. The TGR register and buffer register combinations are TGRA with
TGRC, and TGRB with TGRD.
The TGRs are initialized to H'FFFF by a power-on reset or in standby mode. Manual reset does
not initialize TGR. Accessing of the TGRs in 8-bit units is disabled; they may only be accessed in
16-bit units.
Bit:
15
14
13
12
11
10
9
8
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
12.2.8
Timer Start Register (TSTR)
The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–4. TSTR is initialized to H'00 upon power-on reset or standby
mode. Manual reset does not initialize TSTR.
Bit:
7
6
5
4
3
2
1
0
CST4
CST3
—
—
—
CST2
CST1
CST0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R
R
R
R/W
R/W
R/W
• Bits 7, 6, 2–0—Counter Start 4–0 (CST4–CST0): Select the start and stop of the timer counters
(TCNT). The counter start to channel and bit to channel correspondence are indicated in the
tables below.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com