SH7041A datasheet(483/923 Pages) RENESAS

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12.9.3

Pin Configuration

Table 12.18 shows the POE pins.

Table 12.18 Pin Configuration

Name

Abbreviation

I/O

Description

Port output enable input pins

POE0–POE3

Input

Input request signals to make high-

current pins high-impedance state

Table 12.19 shows output-level comparisons with pin combinations.

Table 12.19 Output Level Comparisons

Pin Combination

I/O

Description

PE09/TIOC3B and

PE11/TIOC3D

Output

All high-current pins are made high-impedance

state when the pins simultaneously output low-level

for longer than 1 cycle.

PE12/TIOC4A and

PE14/TIOC4C/DACK0/

Output

All high-current pins are made high-impedance

state when the pins simultaneously output low-level

for longer than 1 cycle.

PE13/TIOC4B/

MRES and

PE15/TIOC4D/DACK1/

IRQOUT

Output

All high-current pins are made high-impedance

state when the pins simultaneously output low-level

for longer than 1 cycle.

12.9.4

The POE has the two registers shown in table 12.20. The input level control/status register (ICSR)

controls both

POE0–POE3 pin input signal detection and interrupts. The output level

control/status register (OCSR) controls both the enable/disable of output comparison and

interrupts.

Table 12.20 Input Level Control/Status Register Configuration

Name

Abbreviation R/W

Initial Value

Address

Access Size

Input level control/status

ICSR

R/(W)*

H'0000

H'FFFF83C0

H'FFFF83C1

8, 16, 32

Output level

control/status register

OCSR

R/(W)*

H'0000

H'FFFF83C2

H'FFFF83C3

8, 16, 32

Notes: *1 Only 0 writes to bits 15–12 are possible to clear the flags.

*2 Only 0 writes to bits 15 are possible to clear the flags.

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