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SH7041A Datasheet(PDF) 487 Page - Renesas Technology Corp |
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SH7041A Datasheet(HTML) 487 Page - Renesas Technology Corp |
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487 / 923 page  449 12.10.2 Output Level Control/Status Register (OCSR) The output level control/status register (OCSR) is a 16-bit read/write register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance. OCSR is initialized to H'0000 by an external power-on reset; however, it is not initialized for manual resets, reset by WDT standby mode, or sleep mode, so the previous data is maintained. Bit: 15 14 13 12 11 10 9 8 OSF — — — — — OCE OIE Initial value: 0 0 0 0 0 0 0 0 R/W: R/(W)* R R R R R R/W R/W Bit: 7 6 5 4 3 2 1 0 —— —— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Note: * Only 0 writes are possible to clear the flag. • Bit 15—Output Short Flag (OSF): This flag indicates that among the three pairs of 2 phase outputs compared, the outputs of at least one pair have simultaneously become Low level output. Bit 15: OSF Description 0 Clear condition: By writing 0 to OSF after reading an OSF = 1 (initial value) 1 Set condition: When any one pair of the 2-phase outputs simultaneously become Low level • Bits 14–10—Reserved: These bits always read as 0. The write value should always be 0. |
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