SH7041A datasheet(485/923 Pages) RENESAS

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• Bit 13—POE1 Flag (POE1F): This flag indicates that a high impedance request has been input

to the

POE1 pin.

Bit 13: POE1F

Description

Clear condition: By writing 0 to POE1F after reading a POE1F = 1

(initial value)

Set condition: When the input set by ICSR bits 3 and 2 occurs at

the

POE1 pin

• Bit 12—POE0 Flag (POE0F): This flag indicates that a high impedance request has been input

to the

POE0 pin.

Bit 12: POE0F

Description

Clear condition: By writing 0 to POE0F after reading a POE0F = 1

(initial value)

Set condition: When the input set by ICSR bits 1 and 0 occurs at

the

POE0 pin

• Bits 11–9—Reserved: These bits always read as 0. The write value should always be 0.

• Bit 8—Port Interrupt Enable (PIE): Enables or disables interrupt requests when any of the

POE0F–POE3F bits of the ICSR are set to 1.

Bit 8: PIE

Description

Interrupt requests disabled (initial value)

Interrupt requests enabled

• Bits 7 and 6—POE3 Mode 1, 0 (POE3M1 and POE3M0): These bits select the input mode of

the

POE3 pin.

Bit 7:

POE3M1

Bit 6:

POE3M0

Description

Accept request on falling edge of

POE3 input. (initial value)

Accept request when

POE3 input has been sampled for 16

φ/8 clock pulses, and all are low level.

Accept request when

POE3 input has been sampled for 16

φ/16 clock pulses, and all are low level.

Accept request when

POE3 input has been sampled for 16

φ/128 clock pulses, and all are low level.

SH7041A Datasheet(PDF) 485 Page - Renesas Technology Corp

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