SH7041A datasheet(784/923 Pages) RENESAS

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Table 24.3

Module

Registers Initialized

Registers that

Retain Data

Registers with

Undefined Contents

Interrupt controller

(INTC)

—

All registers

—

User break controller

(UBC)

—

All registers

—

Data transfer controller

(DTC)

All registers (excluding transfer

data in memory and DTDR)

——

Cache memory (CAC)

—

All registers

—

Bus state controller

(BSC)

—

All registers

—

Direct memory access

controller (DMAC)

• DMA channel control

registers 0–3 (CHCR0–

CHCR3)

• DMA operation register

(DMAOR)

—

• DMA source

address registers

0–3 (SAR0–

SAR3)

• DMA destination

address registers

0–3 (DAR0–

DAR3)

• DMA transfer

count registers

0–3 (DMATCR0–

DMATCR3)

Multifunction timer

pulse unit (MTU)

MTU associated registers

POE associated

registers

—

Watchdog timer

(WDT)

• Bits 7–5 (OVF, WT/IT, TME)

of the timer control status

• Reset control/status register

(RSTCSR)

• Bits 2–0

(CKS2–CKS0)

of the TCSR

• Timer counter

(TCNT)

—

Serial communication

interface (SCI)

• Receive data register (RDR)

• Transmit data register (TDR)

• Serial mode register (SMR)

• Serial control register (SCR)

• Serial status register (SSR)

• Bit rate register (BBR)

——

A/D converter (A/D)

All registers

—

Compare match timer

(CMT)

All registers

—

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