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SH7041A Datasheet(PDF) 783 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 783 Page - Renesas Technology Corp

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24.3
Sleep Mode
24.3.1
Transition to Sleep Mode
Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the
program execution state to the sleep mode. Although the CPU halts immediately after executing
the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip
peripheral modules continue to run during the sleep mode.
24.3.2
Canceling Sleep Mode
Sleep mode is canceled by an interrupt, DMAC/DTC address error, power-on reset, or manual
reset.
Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt
exception processing is executed. The sleep mode is not canceled if the interrupt cannot be
accepted because its priority level is equal to or less than the mask level set in the CPU’s status
register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral
module.
Cancellation by a DMAC/DTC Address Error: If a DMAC/DTC address error occurs, the sleep
mode is canceled and DMAC/DTC address error exception processing is executed.
Cancellation by a Power-On Reset: A power-on reset resulting from setting the
RES pin to low
level cancels the sleep mode.
Cancellation by a Manual Reset: When the
MRES pin is set to low level while the RES pin is at
high level, a manual reset occurs and the sleep mode is canceled.
24.4
Standby Mode
24.4.1
Transition to Standby Mode
To enter the standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction.
The LSI moves from the program execution state to the standby mode. In the standby mode,
power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip
peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the
prescribed voltages are applied. The register contents of some on-chip peripheral modules are
initialized, but some are not (table 24.3). The I/O port status can be selected as held or high
impedance by the port high impedance bit (HIZ) of the SBYCR. For pin status other than for the
I/O port, refer to Appendix C, Pin States.



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