SH7041A datasheet(218/923 Pages) RENESAS

218 / 923 page

180

• Bits 11–10—DRAM Write Cycle Wait Count (DWW1–DWW0): Specifies the number of

DRAM write cycle column address output cycles.

Bit 11 (DWW1)

Bit 10 (DWW0)

Description

2-cycle (no wait) external wait disabled

(initial value)

3-cycle (1 wait) external wait disabled

4-cycle (2 wait) external wait enabled

5-cycle (3 wait) external wait enabled

• Bits 9–8—DRAM Read Cycle Wait Count (DWR1–DWR0): Specifies the number of DRAM

read cycle column address output cycles.

Bit 9 (DWR1)

Bit 8 (DWR0)

Description

2-cycle (no wait) external wait disabled

(initial value)

3-cycle (1 wait) external wait disabled

4-cycle (2 wait) external wait enabled

5-cycle (3 wait) external wait enabled

• Bit 7—DRAM Idle Cycle Count (DIW): Specifies whether to insert idle cycles, either when

accessing a different external space (CS space) or when doing a DRAM write, after DRAM

reads.

Bit 7 (DIW)

Description

No idle cycles (initial value)

1 idle cycle

• Bit 6—Reserved: This bit always reads as 0. The write value should always be 0.

• Bit 5—Burst Enable (BE): Specifies the DRAM operation mode.

Bit 5 (BE)

Description

Burst disabled (initial value)

DRAM high-speed page mode enabled

• Bit 4—RAS Down Mode (RASD): Specifies the DRAM operation mode.

Bit 4 (RASD)

Description

Access DRAM by RAS up mode (initial value)

Access DRAM by RAS down mode

SH7041A Datasheet(PDF) 218 Page - Renesas Technology Corp