SH7041A datasheet(219/923 Pages) RENESAS

Part #	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

219 / 923 page

181

• Bits 3–2—DRAM Bus Width Specification (SZ1, SZ0): Specifies the DRAM space bus width.

Bit 3 (SZ1)

Bit 2 (SZ0)

Description

Byte (8 bits)

(initial value)

Word (16 bits)

Don’t care

Longword (32 bits)

• Bits 1–0—DRAM Address Multiplex (AMX1–AMX0): Specifies the DRAM address

multiplex count.

Bit 1 (AMX1)

Bit 0 (AMX0)

Description

9 bit

(initial value)

10 bit

11 bit

12 bit

10.2.6

Refresh Timer Control/Status Register (RTCSR)

RTCSR is a 16-bit read/write register that selects the refresh mode and the clock input to the

refresh timer counter (RTCNT), and controls compare match interrupts (CMI).

RTCSR is initialized by power-on resets and hardware standbys to H'0000, but is not initialized by

manual resets or software standbys.

Bit:

——

———

—

Initial value:

R/W:

Bit:

—

CMF

CMIE

CKS2

CKS1

CKS0

RFSH

RMD

Initial value:

R/W:

R/W

• Bits 15–7—Reserved: These bits always read as 0. The write value should always be 0.

SH7041A Datasheet(PDF) 219 Page - Renesas Technology Corp

SH7041A Datasheet(HTML) 219 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL