SH7041A datasheet(220/923 Pages) RENESAS

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• Bit 6—Compare Match Flag (CMF): This status flag, which indicates that the values of

RTCNT and RTCOR match, is set/cleared under the following conditions:

Bit 6 (CMF)

Description

Clear condition: After RTCSR is read when CMF is 1, 0 is written in

CMF. In some cases it will clear when DTC is activated by a compare

match interrupt; refer to section 8, Data Transfer Controller (DTC), for

details. (initial value)

Set condition: RTCNT = RTCOR. When both RTCNT and RTCOR are

in an initialized state (when values have not been rewritten since

initialization, and RTCNT has not had its value changed due to a count-

up), RTCNT and RTCOR match, as both are H'0000, but in this case

CMF is not set.

• Bit 5—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request

caused by the CMF bit of the RTCSR when CMF is set to 1.

Bit 5 (CMIE)

Description

Disables an interrupt request caused by CMF (initial value)

Enables an interrupt request caused by CMF

• Bits 4–2—Clock Select (CKS2–CKS0): Select the clock to input to RTCNT from among the

seven types of internal clock obtained from dividing the system clock (

φ).

Bit 4 (CKS2)

Bit 3 (CKS1)

Bit 2 (CKS0)

Description

Stops count-up (initial value)

φ/2

φ/8

φ/32

φ/128

φ/512

φ/2048

φ/4096

• Bit 1—Refresh Control (RFSH): Selects whether to use refresh control for DRAM.

Bit 1 (RFSH)

Description

Do not refresh DRAM (initial value)

Refresh DRAM

SH7041A Datasheet(PDF) 220 Page - Renesas Technology Corp