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SH7041A Datasheet(PDF) 321 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 321 Page - Renesas Technology Corp

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283
12.2
MTU Register Descriptions
12.2.1
Timer Control Register (TCR)
The TCR is an 8-bit read/write register for controlling the TCNT counter for each channel. The
MTU has five TCR registers, one for each of the channels 0 to 4. TCR is initialized to H'00 by a
power-on reset or the standby mode. Manual reset does not initialize TCR.
Channels 0, 3, 4: TCR0, TCR3, TCR4:
Bit:
7
6
5
4
3
2
1
0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channels 1, 2: TCR1, TCR2:
Bit:
7
6
5
4
3
2
1
0
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Bits 7–5—Counter Clear 2, 1, 0 (CCLR2, CCLR1, CCLR0): Select the counter clear source for
the TCNT counter.



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