SH7041A datasheet(326/923 Pages) RENESAS

Part #	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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12.2.2

Timer Mode Register (TMDR)

The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU

has five TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset

or the standby mode. Manual reset does not initialize TMDR.

Channels 0, 3, 4: TMDR0, TMDR3, TMDR4:

Bit:

—

BFB

BFA

MD3

MD2

MD1

MD0

Initial value:

R/W:

R/W

Channels 1, 2: TMDR1, TMDR2:

Bit:

—

MD3

MD2

MD1

MD0

Initial value:

R/W:

R/W

• Bits 7, 6—Reserved: These bits are reserved. They always read as 1, and cannot be modified.

• Bit 5—Buffer Operation B (BFB): Designates whether to use the TGRB register for normal

operation, or buffer operation in combination with the TGRD register. When using TGRD as a

buffer register, no TGRD register input capture/output compares are generated.

This bit is reserved in channels 1 and 2, which have no TGRD registers. It is always read as 0,

and cannot be modified.

Bit 5: BFB

Description

TGRB operates normally (initial value)

TGRB and TGRD buffer operation

SH7041A Datasheet(PDF) 326 Page - Renesas Technology Corp