SH7041A datasheet(327/923 Pages) RENESAS

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• Bit 4—Buffer Operation A (BFA): Designates whether to use the TGRA register for normal

operation, or buffer operation in combination with the TGRC register. When using TGRC as a

buffer register, no TGRC register input capture/output compares are generated.

This bit is reserved in channels 1 and 2, which have no TGRC registers. It is always read as 0,

and cannot be modified.

Bit 4: BFA

Description

TGRA operates normally (initial value)

TGRA and TGRC buffer operation

• Bits 3–0—Modes 3–0 (MD3–MD0): These bits set the timer operation mode.

Bit 3:

MD3

Bit 2:

MD2

Bit 1:

MD1

Bit 0:

MD0

Description

0000

Normal operation (initial value)

Reserved (do not set)

PWM mode 1

PWM mode 2*

Phase counting mode 1*

Phase counting mode 2*

Phase counting mode 3*

Phase counting mode 4*

1000

Reset synchronous PWM mode*

Reserved (do not set)

Complementary PWM mode 1 (transmit at peak)*

Complementary PWM mode 2 (transmit at valley)*

Complementary PWM mode 3 (transmit at peak and valley) *

Notes: *1 PWM mode 2 can not be set for channels 3, 4.

*2 Phase measurement mode can not be set for channels 0, 3, 4.

*3 Reset synchronous PWM mode, complementary PWM mode can only be set for

channel 3. When channel 3 is set to reset synchronous PWM mode or complementary

PWM mode, the channel 4 settings become ineffective and automatically conform to the

channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or

complementary PWM mode. Reset synchronous PWM mode and complementary PWM

mode can not be set for channels 0, 1, 2.

SH7041A Datasheet(PDF) 327 Page - Renesas Technology Corp

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