FEDL7716P-01

OKI Semiconductor

MSM7716P

9/23

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Power Supply Voltage

AG = DG = 0 V

–0.3 to +7.0

V

Analog Input Voltage

AG = DG = 0 V

V

Digital Input Voltage

AG = DG = 0 V

V

Storage Temperature

—

–55 to +150

°C

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Voltage

—

3.0

3.3

3.6

V

Operating Temperature

Ta

—

–40

+25

+85

°C

Analog Input Voltage

Gain = 1

—

—

1.4

High Level Input Voltage

0.45

×V

D

D

—

V

Low Level Input Voltage

SYNC, BCLK, PCMIN, PDN,

DEN, DCLK, CDIN

0

—

0.16

×V

D

D

V

Clock Frequency

BCLK

14

× F

S

—

128

× F

S

kHz

Sync Pulse Frequency

SYNC

4.0

8.0

16

kHz

Clock Duty Ratio

BCLK

40

50

60

%

Digital Input Rise Time

—

—

50

ns

Digital Input Fall Time

SYNC, BCLK, PCMIN, PDN,

DEN, DCLK, CDIN

—

—

50

ns

100

—

—

ns

Sync Pulse Setting Time

100

—

—

ns

High Level Sync Pulse Width *1

SYNC, See Fig. 1

1 BCLK

—

—

—

Low Level Sync Pulse Width *1

SYNC, See Fig. 1

1 BCLK

—

—

—

PCMIN Setup Time

Refer to Fig. 1

100

—

—

ns

PCMIN Hold Time

Refer to Fig. 1

100

—

—

ns

Pull-up resistor

0.5

—

—

k

Ω

Digital Output Load

—

—

—

100

pF

DCLK Low width, See Fig. 2

50

—

—

DCLK Pulse Width

DCLK High width, See Fig. 2

50

—

—

ns

DCLK

→ DEN, See Fig. 2

50

—

—

DEN Setting Time 1

DEN

→ DCLK, See Fig. 2

50

—

—

ns

DCLK

→ DEN, See Fig. 2

50

—

—

DEN Setting Time 2

DEN

→ DCLK, See Fig. 2

50

—

—

ns

CDIN Setup Time

See Fig. 2

50

—

—

CDIN Hold Time

See Fig. 2

50

—

—

ns

Transmit gain stage, Gain = 0 dB

–100

—

+100

mV

Analog Input Allowable DC Offset

Transmit gain stage, Gain = 20 dB

–10

—

+10

mV

Allowable Jitter Width

—

SYNC, BCLK

—

—

1000

ns

*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz.