STM32H750VB datasheet(1/335 Pages) STMICROELECTRONICS

Part #	STM32H750VB

Description	32-bit Arm® Cortex®-M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto

PDF	335 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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1 / 335 page

This is information on a product in full production.

November 2019

DS12556 Rev 5

1/334

STM32H750VB STM32H750ZB

STM32H750IB STM32H750XB

32-bit Arm® Cortex®-M7 480MHz MCUs, 128 Kbyte Flash,

1 Mbyte RAM, 46 com. and analog interfaces, crypto

Datasheet

- production data

Features

Core

 32-bit Arm® Cortex®-M7 core with double-

precision FPU and L1 cache: 16 Kbytes of data

and 16 Kbytes of instruction cache; frequency

up to 480 MHz, MPU, 1027 DMIPS/

2.14 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

Memories

 128 Kbytes of Flash memory

 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.

64 Kbytes of ITCM RAM + 128 Kbytes of

DTCM RAM for time critical routines),

864 Kbytes of user SRAM, and 4 Kbytes of

SRAM in Backup domain

 Dual mode Quad-SPI memory interface

running up to 133 MHz

 Flexible external memory controller with up to

32-bit data bus:

– SRAM, PSRAM, NOR Flash memory

clocked up to 133 MHz in synchronous

mode

– SDRAM/LPSDR SDRAM

– 8/16-bit NAND Flash memories

 CRC calculation unit

Security

 ROP, PC-ROP, active tamper, secure firmware

upgrade support, Secure access mode

General-purpose input/outputs

 Up to 168 I/O ports with interrupt capability

Reset and power management

 3 separate power domains which can be

independently clock-gated or switched off:

– D1: high-performance capabilities

– D2: communication peripherals and timers

– D3: reset/clock control/power management

 1.62 to 3.6 V application supply and I/Os

 POR, PDR, PVD and BOR

 Dedicated USB power embedding a 3.3 V

internal regulator to supply the internal PHYs

 Embedded regulator (LDO) with configurable

scalable output to supply the digital circuitry

 Voltage scaling in Run and Stop mode (6

configurable ranges)

 Backup regulator (~0.9 V)

 Voltage reference for analog peripheral/VREF+

 Low-power modes: Sleep, Stop, Standby and

VBAT supporting battery charging

Low-power consumption

 VBAT battery operating mode with charging

capability

 CPU and domain power state monitoring pins

 2.95 µA in Standby mode (Backup SRAM OFF,

RTC/LSE ON)

Clock management

 Internal oscillators: 64 MHz HSI, 48 MHz

HSI48, 4 MHz CSI, 32 kHz LSI

 External oscillators: 4-48 MHz HSE,

32.768 kHz LSE

 3× PLLs (1 for the system clock, 2 for kernel

clocks) with Fractional mode

FBGA

LQFP100

(14 x 14 mm)

LQFP144

(20 x 20 mm)

LQFP176

(24 x 24 mm)

UFBGA176+25

(10x10 mm)

FBGA

TFBGA240+25

(14x14 mm)

www.st.com

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