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STM32H750VB Datasheet(PDF) 267 Page - STMicroelectronics |
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STM32H750VB Datasheet(HTML) 267 Page - STMicroelectronics |
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267 / 335 page ![]() DS12556 Rev 5 267/334 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Electrical characteristics (rev V) 311 Figure 86. Quad-SPI timing diagram - SDR mode Figure 87. Quad-SPI timing diagram - DDR mode 7.3.19 Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 181 for Delay Block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 120: General operating conditions, with the following configuration: MSv36878V1 Data output D0 D1 D2 Clock Data input D0 D1 D2 t(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) ts(IN) th(IN) tv(OUT) th(OUT) MSv36879V3 Data output IO0 IO2 IO4 Clock Data input IO0 IO2 IO4 t(CLK) tw(CLKH) tw(CLKL) tr(CLK) tf(CLK) tsf(IN) thf(IN) tvf(OUT) thr(OUT) IO1 IO3 IO5 IO1 IO3 IO5 tvr(OUT) thf(OUT) tsr(IN) thr(IN) Table 181. Delay Block characteristics Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 1400 2200 2400 ps t∆ Unit Delay - 35 40 45 - |
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