2

Copyright © 2018 Everspin Technologies

MR25H256 / MR25H256A Rev. 1.5 3/2018

MR25H256 / MR25H256A

TABLE OF CONTENTS

OVERVIEW ............................................................................................................................................4

Figure 1 – Block Diagram........................................................................................................................................... 4

System Configuration .....................................................................................................................4

Figure 2 – System Configuration............................................................................................................................. 4

DEVICE PIN ASSIGNMENT...................................................................................................................5

Figure 3 – Pin Diagram All 8-DFN Packages........................................................................................................ 5

Table 1 – Pin Functions All 8-DFN Packages ....................................................................................................... 5

SPI COMMUNICATIONS PROTOCOL...................................................................................................6

Table 2 – Command Codes ....................................................................................................................................... 6

Status Register and Block Write Protection ..................................................................................6

Table 3 – Status Register Bit Assignments........................................................................................................... 6

Table 4 – Block Memory Write Protection............................................................................................................ 7

Table 5 – Memory Protection Modes .................................................................................................................... 7

Read Status Register (RDSR)...........................................................................................................7

Figure 4 – RDSR ............................................................................................................................................................. 7

Write Enable (WREN).......................................................................................................................8

Figure 5 – WREN............................................................................................................................................................ 8

Write Disable (WRDI).......................................................................................................................8

Figure 6 – WRDI ............................................................................................................................................................. 8

Write Status Register (WRSR) .........................................................................................................9

Figure 7 – WRSR............................................................................................................................................................. 9

Read Data Bytes (READ) ............................................................................................................... 10

Figure 8 – READ...........................................................................................................................................................10

Write Data Bytes (WRITE)............................................................................................................. 11

Figure 9 – WRITE..........................................................................................................................................................11

Enter Sleep Mode (SLEEP)............................................................................................................ 12

Figure 10 – SLEEP........................................................................................................................................................12