12 Layout

12.1 Layout Guidelines

In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much

overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high

di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout.

It is advantageous to connect the driver IC as close as possible to the leads. The driver device layout has the

analog ground on the opposite side of the output, so the ground should be connected to the bypass capacitors

and the load with copper trace as wide as possible. These connections should also be made with a small

enclosed loop area to minimize the inductance.

12.2 Layout Example

14

UCD91xx

with

CLA

Peripheral

1

12

8

PVDD

OUT

CS

10

PGND

3

4

2

5

6

3V3

AGND

IN

CLF

ILIM

7

2

UCD7100PWP

Bias

Winding

VIN

VOUT

VDS

CS

FB

CS

VDS

COMMUNICATION

(Programming & Status Reporting)

Bias Supply

11

OUT

9

PGND

13

PVDD

VDD

NC

2

Isolation

Amplifier

2

1

Figure 12-1. Isolated Forward Converter

UCD7100

SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021

www.ti.com

18

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