TMUX7308FRRPR datasheet(6/54 Pages) TI

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7.3 Thermal Information

THERMAL METRIC(1)

TMUX7308F/ TMUX7309F

UNIT

PW (TSSOP)

RRP (QFN)

16 PINS

RθJA

Junction-to-ambient thermal resistance

100.4

43.0

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

31.3

28.8

°C/W

RθJB

Junction-to-board thermal resistance

46.4

17.9

°C/W

ΨJT

Junction-to-top characterization parameter

1.7

0.4

°C/W

ΨJB

Junction-to-board characterization parameter

45.8

17.9

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

4.2

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

VDD – VSS (1) Power supply voltage differential

VDD

Positive power supply voltage

Source pin (Sx) voltage (non-fault condition)

VSS

VDD

VS to GND

Source pin (Sx) voltage to GND (fault condition)

–60

VS to VDD (2)

Source pin (Sx) voltage to VDD or VD (fault condition)

–85

VS to VSS (2)

Source pin (Sx) voltage to VSS or VD (fault condition)

Drain pin (D, Dx) voltage

VSS

VDD

VEN or VAx

Logic control input pin voltage (EN, A0, A1, A2)

Ambient temperature

–40

125

°C

IDC

Continuous current through switch

TA = 25°C

TA = 85°C

6.5

TA = 125°C

(1)

VDD and VSS can be any value as long as 8 V ≤ (VDD – VSS) ≤ 44 V, and the minimum VDD is met.

(2)

Under a fault condition, the potential difference between source pin (Sx) and supply pins (VDD and VSS.) or source pin (Sx) and drain

pins (D, Dx) may not exceed 85 V.

7.5 Electrical Characteristics (Global)

at TA = 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG SWITCH

Threshold voltage for fault

detector

25°C

0.7

LOGIC INPUT/ OUTPUT

VIH

High-level input voltage

EN, Ax pins

–40°C to +125°C

1.3

VIL

Low-level input voltage

EN, Ax pins

–40°C to +125°C

0.8

POWER SUPPLY

VUVLO

Undervoltage lockout (UVLO)

threshold voltage (VDD – VSS)

Rising edge, single supply

–40°C to +125°C

5.1

6.4

Undervoltage lockout (UVLO)

threshold voltage (VDD – VSS)

Falling edge, single supply

–40°C to +125°C

5.8

6.3

VHYS

VDD Undervoltage

lockout (UVLO) hysteresis

Single supply

–40°C to +125°C

0.2

RD(OVP)

Drain resistance to supply rail during overvoltage event on selected source pin 25°C

kΩ

TMUX7308F, TMUX7309F

SCDS403B – FEBRUARY 2021 – REVISED DECEMBER 2021

www.ti.com

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