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TMS28F004ASB80CDCDL Datasheet(PDF) 40 Page - Texas Instruments |
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TMS28F004ASB80CDCDL Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 80 page  TMS28F004Axy, TMS28F400Axy 524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES SMJS829A – JANUARY 1996 – REVISED AUGUST 1997 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements for TMS28F004AEy and TMS28F400AEy write/erase operations — W-controlled writes ALT ’28F004AEy 60 ’28F400AEy 60 ALT. SYMBOL 3-V VCC RANGE 5-V VCC RANGE UNIT MIN MAX MIN MAX tc( W ) Cycle time, write tAVAV 110 60 ns tc( W )OP Cycle time, duration of programming operation tWHQV1 6 6 µs tc( W )ERB Cycle time, erase operation (boot block) tWHQV2 0.3 0.3 s tc( W )ERP Cycle time, erase operation (parameter block) tWHQV3 0.3 0.3 s tc( W )ERM Cycle time, erase operation (main block) tWHQV4 0.6 0.6 s td(RPR) Delay time, boot-block relock tPHBR 200 100 ns th(A) Hold time, A0 – A17 (see Note 15) tWHAX 0 0 ns th(D) Hold time, DQ valid tWHDX 0 0 ns th(E) Hold time, E tWHEH 0 0 ns th( VPP) Hold time, VPP from valid status register bit tQVVL 0 0 ns th(RP) Hold time, RP at VHH from valid status register bit tQVPH 0 0 ns th(WP) Hold time, WP from valid status register bit tWHPL 0 0 ns tsu(WP) Setup time, WP before write operation tELPH 90 50 ns tsu(A) Setup time, A0 – A17 (see Note 15) tAVWH 90 50 ns tsu(D) Setup time, DQ tDVWH 90 50 ns tsu(E) Setup time, E before write operation tELWL 0 0 ns tsu(RP) Setup time, RP at VHH to W going high tPHHWH 200 100 ns tsu( VPP)1 Setup time, VPP to W going high tVPWH 200 100 ns tw( W ) Pulse duration, W low tWLWH 90 50 ns tw( WH) Pulse duration, W high tWHWL 20 10 ns trec(RPHW) Recovery time, RP high to W going low tPHWL 800 450 ns NOTE 15: A–1 – A17 for byte-wide |
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