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AS4LC2M8S1 Datasheet(PDF) 5 Page - Alliance Semiconductor Corporation |
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AS4LC2M8S1 Datasheet(HTML) 5 Page - Alliance Semiconductor Corporation |
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5 / 29 page ![]() ® AS4LC2M8S1 AS4LC1M16S1 5/21/01; v.1.1 Alliance Semiconductor P. 5 of 29 Mode register fields † RFU = 0 during MRS cycle. Burst sequence (burst length = 4) Burst sequence (burst length = 8) Register programmed with MRS Address A11~A10 A9A8A7 A6 A5 A4A3 A2 A1 A0 Function RFU† WBL TM CAS latency BT Burst length Write burst length Burst type A9 Length A3 Type 0 Programmed burst length 0 Sequential 1Interleaved 1Single burst Test mode A8 A7 Type 0 0 Mode register set 01 Reserved 10 Reserved 11 Reserved CAS latency Burst length A6 A5 A4 Latency A2 A1 A0 BT = 0 BT = 1 0 0 0 Reserved 0 001 1 0 0 1 1 0 012 2 0 1 0 2 0 104 4 0 1 1 3 0 118 8 1 X X Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 11 1 Full page Reserved Initial address Sequential Interleave A1 A0 0 0 01 23 01 23 0 1 12 30 10 32 1 0 23 01 23 01 1 1 30 12 32 10 Initial address Sequential Interleave A2 A1 A0 0 0 0 0123456701234567 0 0 1 1234567010325476 0 1 0 2345670123016745 0 1 1 3456701232107654 1 0 0 4567012345670123 1 0 1 5670123454761032 1 1 0 6701234567452301 1 1 1 7012345676543210 |
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