MIC826

DS20006668A-page 8



2022 Microchip Technology Inc. and its subsidiaries

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Pin Name

Description

1

/RESET

Active-Low Reset Output. Pulses low for 200 ms when triggered, and remains low

watchdog triggers a reset, or /MR goes low to high.

2

GND

Supply Ground.

3

RESET

Active-High Reset Output. Pulses high for 200 ms when triggered, and remains high

threshold, the watchdog triggers a reset, or /MR goes low to high. RESET is the

inverse of /RESET.

4

WDI

Watchdog Input. If WDI remains either high or low for longer than the watchdog

timeout period, the internal watchdog timer runs out and a reset is triggered. The

internal watchdog timer clears whenever reset is asserted, or whenever WDI sees a

rising or falling edge. If WDI is left unconnected or is connected to a three-stated

buffer output, the watchdog feature is disabled.

5

/MR

Manual Reset Input. A logic low on /MR asserts reset. Reset remains asserted as

long as /MR is held low and for 200 ms after /MR returns high. The active-low input

has an internal 52 kΩ pull-up resistor. It can be driven from a CMOS logic line or

shorted to ground with a switch. Leave open or connect to VCC if unused.

6

VCC

Supply Voltage Pin. VCC is the input to the supply voltage monitor. When the supply

voltage falls below the reset threshold voltage, reset outputs (/RESET and RESET)

are triggered immediately. When the supply voltage rises above the reset threshold

plus hysteresis voltage, the reset outputs remain asserted for the duration of the

reset timeout period. A decoupling ceramic capacitor (minimum 0.1 μF) must be

connected between VCC and GND close to the pins.

EP

ePAD

Exposed Pad. Connect to GND.