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MPC8358ECVRAGDDA Datasheet(PDF) 76 Page - NXP Semiconductors |
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MPC8358ECVRAGDDA Datasheet(HTML) 76 Page - NXP Semiconductors |
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76 / 95 page  MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 76 Freescale Semiconductor Clocking 22.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. Table 68 shows the multiplication factor encodings for the system PLL. The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 69. NOTE The VCO divider must be set properly so that the system VCO frequency is in the range of 600–1400 MHz. Table 68. System PLL Multiplication Factors RCWL[SPMF] System PLL Multiplication Factor 0000 × 16 0001 Reserved 0010 × 2 0011 × 3 0100 × 4 0101 × 5 0110 × 6 0111 × 7 1000 × 8 1001 × 9 1010 × 10 1011 × 11 1100 × 12 1101 × 13 1110 × 14 1111 × 15 Table 69. System PLL VCO Divider RCWL[SVCOD] VCO Divider 00 4 01 8 10 2 11 Reserved |
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