ADM1041 datasheet(21/64 Pages) AD

21 / 64 page

ADM1041

Rev. A | Page 21 of 64

0123

VOLTAGE (V)

Figure 10. Current Limit

0.75

1.00

2.25

2.00

1.25

0.50

0.25

1.50

1.75

2.75

2.50

100

10k

100k

10M

100M

BANDWIDTH

Figure 11. VCMP Transconductance

180

160

100

120

140

220

200

100

10k

100k

10M

100M

BANDWIDTH

Figure 12. CCMP and SCMP Transconductance

VOLTAGE ERROR AMPLIFIER

This is a high gain transconductance amplifier that takes its

input from the load voltage trim stage described previously. The

amplifier requires only the output pin for loop compensation,

which typically consists of a series RC network-to-common. A

parallel resistor may be added to common to reduce the open-

loop gain and thereby provide some output voltage droop as

output current increases. The output of the amplifier is typically

connected to an emitter follower that drives an optocoupler,

which in turn controls the duty of the primary side PWM. The

emitter follower should have a high gain to minimize loading

effects on the amplifier. Alternatively, an op amp voltage

follower may be used. See Figure 9, Figure 10, and Figure 11.

MAIN VOLTAGE REFERENCE

A 1.5 V reference is connected to the inverting input of the

voltage error amplifier. This 1.5 V reference is the output voltage

of the soft-start circuit. Under closed-loop conditions, the

voltage at the noninverting input is also controlled to 1.5 V.

During start-up, the output voltage should be ramped up in a

linear fashion at a rate that is independent of the load current.

This is achieved by digitally ramping up the reference voltage by

using a counter and a DAC. The ramp rate is configurable via

the SMBus. See Figure 14.

CURRENT SENSE AMPLIFIER

This is a two-stage differential amplifier that achieves low offset

and accuracy. The amplifier has the option to be chopped to

reduce offset or left as a linear amplifier without chopping.

Refer to the Register Listing for more details. Its gain may be

selected from three ranges. It is followed by a trim stage and

then by a low gain buffer stage that can be configured with a

gain of 1.0 or 2.1. The result is a total of six overlapping gain

ranges (65 to 230), one of which must be selected via the SMBus.

This gives ample adjustment to compensate for the poor initial

tolerance of the resistance wires typically used for current

sensing. It also allows selecting a higher sensitivity for better

efficiency or a lower sensitivity for better accuracy (lower offset).

The amplifier offset voltage is trimmed to zero in a once-off

operation via the SMBus and uses a voltage controlled current

source at the output of the first gain stage. A second controlled

current source is used to trim out the additional offset due to

the mismatch of the external divider resistors. This offset trim is

dynamically adjusted according to the common-mode voltage

present at the top of the voltage dividers. Six ranges are selectable

according to the magnitude and polarity of this offset component.

Because the offset compensation circuit itself has some inaccu-

racies, the best overall current sense accuracy is obtained by

using more closely matched external dividers and then selecting

a low compensation range. See Figure 14.

ADM1041 Datasheet(PDF) 21 Page - Analog Devices

ADM1041 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL