PIC18F2450-ESLASHML datasheet(41/320 Pages) MICROCHIP

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PIC18F2450/4450

Advance Information

DS39760A-page 39

3.4.3

RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the periph-

erals continue to be clocked from the internal oscillator,

INTRC. This mode allows for controllable power

conservation during Idle periods.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in another Run mode, first set IDLEN, then set

the SCS1 bit and execute SLEEP. Although its value is

ignored, it is recommended that SCS0 also be cleared;

this is to maintain software compatibility with future

devices. When the clock source is switched to the

INTRC, the primary oscillator is shut down and the

OSTS bit is cleared.

When a wake event occurs, the peripherals continue to

be clocked from the INTRC. After a delay of TCSD fol-

lowing the wake event, the CPU begins executing code

being clocked by the INTRC. The IDLEN and SCS bits

are not affected by the wake-up. The INTRC source will

continue to run if either the WDT or the Fail-Safe Clock

Monitor is enabled.

3.5

Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is

triggered by an interrupt, a Reset or a WDT time-out.

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

modes (see Section 3.2 “Run Modes”, Section 3.3

“Sleep Mode” and Section 3.4 “Idle Modes”).

3.5.1

EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode, or the Sleep mode, to

a Run mode. To enable this functionality, an interrupt

source must be enabled by setting its enable bit in one

of the INTCON or PIE registers. The exit sequence is

initiated when the corresponding interrupt flag bit is set.

On all exits from Idle or Sleep modes by interrupt, code

execution branches to the interrupt vector if the GIE/

GIEH bit (INTCON<7>) is set. Otherwise, code execution

continues

resumes

without

branching

(see

Section 8.0 “Interrupts”).

A fixed delay of interval TCSD, following the wake event,

is required when leaving Sleep and Idle modes. This

delay is required for the CPU to prepare for execution.

Instruction execution resumes on the first clock cycle

following this delay.

3.5.2

EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in an exit from the

power-managed

mode

(see

Section 3.2

“Run

Modes” and Section 3.3 “Sleep Mode”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 18.2 “Watchdog

Timer (WDT)”).

3.5.3

EXIT BY RESET

Normally, the device is held in Reset by the Oscillator

Start-up Timer (OST) until the primary clock becomes

ready. At that time, the OSTS bit is set and the device

begins executing code.

The exit delay time from Reset to the start of code

execution depends on both the clock sources before

and after the wake-up and the type of oscillator if the

new clock source is the primary clock. Exit delays are

summarized in Table 3-2.

Code execution can begin before the primary clock

becomes ready. If either the Two-Speed Start-up (see

Section 18.3 “Two-Speed Start-up”) or Fail-Safe

Clock Monitor (see Section 18.4 “Fail-Safe Clock

Monitor”) is enabled, the device may begin execution

as soon as the Reset source has cleared. Execution is

clocked by the INTRC driven by the internal oscillator.

Execution is clocked by the internal oscillator until

either the primary clock becomes ready or a power-

managed mode is entered before the primary clock

becomes ready; the primary clock is then shut down.

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