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PIC18F2450-E/ML Datasheet(PDF) 13 Page - Microchip Technology |
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PIC18F2450-E/ML Datasheet(HTML) 13 Page - Microchip Technology |
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13 / 320 page  PIC18F2450/4450 © 2006 Microchip Technology Inc. Advance Information DS39760A-page 11 FIGURE 1-2: PIC18F4450 (40/44-PIN) BLOCK DIAGRAM Instruction Decode & Control Data Latch Data Memory (2 Kbytes) Address Latch Data Address<12> 12 Access BSR 44 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (24/32 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 ROM Latch PORTD PCLATU PCU PORTE MCLR/VPP/RE3(1) RE2/AN7 RE0/AN5 RE1/AN6 Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated Packages Only)” for additional information. EUSART 10-bit ADC Timer2 Timer1 Timer0 CCP1 W Instruction Bus <16> STKPTR Bank 8 State Machine Control Signals 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(2) OSC2(2) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Reference Band Gap VSS MCLR(1) Block INTRC Oscillator Single-Supply Programming In-Circuit Debugger T1OSI T1OSO PORTA PORTB PORTC RA4/T0CKI/RCV RA5/AN4/HLVDIN RB0/AN12/INT0 RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO OSC2/CLKO/RA6 RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD USB FSR0 FSR1 FSR2 inc/dec Address 12 Decode logic USB Voltage Regulator VUSB ICRST(3) ICPGC(3) ICPGD(3) ICPORTS(3) RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 BOR HLVD |
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