R5F5671CDDBP datasheet(4/178 Pages) RENESAS

4 / 178 page

RX671 Group

1. Overview

R01DS0373EJ0110 Rev.1.10

Page 4 of 178

Apr 15, 2022

Low power

consumption

Low power consumption

function

• Module stop function

• Four low power consumption modes

Sleep mode, all-module clock stop mode, software standby mode, and deep software

standby mode

Battery backup function

• When the voltage on the VCC pin drops, power can be supplied to the backup power

area from the VBATT pin.

• Backup power area:

Sub-clock oscillator

Realtime clock

Backup register

Tamper detection

• Detection of low voltage in the backup power area

Interrupt

Interrupt controller

(ICUE)

• Peripheral function interrupts: 256 sources

• External interrupts: 16 (pins IRQ0 to IRQ15)

• Software interrupts: 2 sources

• Non-maskable interrupts: 8 sources

• Sixteen levels specifiable for the order of priority

• Method of interrupt source selection:

The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 133

vectors are selected from among the other 128 sources.)

External bus extension

• The external address space can be divided into eight areas (CS0 to CS7), each with

independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7)

A chip-select signal (CS0# to CS7#) can be output for each area.

Each area is specifiable as an 8-, or 16-bit bus space.

The data arrangement in each area is selectable as little or big endian (only for data).

• SDRAM interface connectable

• Bus format: Separate bus, multiplex bus

• Wait control

• Write buffer facility

DMA

DMA controller

(DMACAb)

• 8 channels

• Three transfer modes: Normal transfer, repeat transfer, and block transfer

• Activation sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

• Transfer space: 4 Gbytes (0000 0000h to FFFF FFFFh excluding reserved areas)

EXDMA controller

(EXDMACa)

• 2 channels

Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster

transfer

• Single-address transfer enabled with the EDACKn signal

• Request sources: Software trigger, external DMA requests (EDREQn), and interrupt

requests from peripheral functions

Data transfer controller

(DTCb)

• Three transfer modes: Normal transfer, repeat transfer, and block transfer

• Request sources: External interrupts and interrupt requests from peripheral functions

• Sequence transfer

Table 1.1

Outline of Specifications (3/10)

Classification

Module/Function

Description

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