ESP32-S2 datasheet(30/51 Pages) ESPRESSIF

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Functional Description

• able to read real-time value of the time-base counter

• halting and resuming the time-base counter

• programmable alarm generation

• timer value reload (Auto-reload at alarm or software-controlled instant reload)

• level and edge interrupt generation

3.7.2 Watchdog Timers

The ESP32-S2 contains three watchdog timers: one in each of the two timer groups (called Main System

Watchdog Timers, or MWDT) and one in the RTC Module (called the RTC Watchdog Timer, or RWDT). Each

watchdog timer allows for four separately configurable stages and each stage can be programmed to take one of

three (or four for RWDT) actions upon expiry, unless the watchdog is fed or disabled. The actions upon expiry

are: interrupt, CPU reset, core reset and system reset. Only RWDT can trigger a system reset that will reset the

entire digital circuits, which is the main system including the RTC itself. A timeout value can be set for each stage

individually.

During the flash boot process, RWDT and the first MWDT are enabled automatically in order to detect and

recover from booting errors.

Watchdog timers have the following features:

• four stages, each with a programmable timeout value. Each stage can be configured and enabled/disabled

separately

• one of three/four (for MWDTs/ RWDT) possible actions (interrupt, CPU reset, core reset and system reset)

available upon expiry of each stage

• 32-bit expiry counter

• write protection, to prevent RWDT and MWDT configuration from being altered inadvertently

• flash boot protection

If the boot process from an SPI flash does not complete within a predetermined period of time, the

watchdog will reboot the entire main system.

3.8 Cryptographic Hardware Accelerators

ESP32-S2 is equipped with hardware accelerators of general algorithms, such as AES (FIPS PUB 197),

ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), GCM (NIST SP 800-38D), SHA (FIPS PUB 180-4), and RSA,

which support independent arithmetic, such as Big Integer Multiplication and Big Integer Modular Multiplication.

The maximum operation length for RSA, Big Integer Multiplication and Big Integer Modular Multiplication is 4096

bits. The maximum factor length for Big Integer Multiplication is 2048 bits.

3.9 Physical Security Features

• Transparent external flash and RAM encryption (AES-XTS) with software inaccessible key prevents

unauthorized readout of user application code or data.

• Secure Boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature)

can be booted.

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ESP32-S2 Series Datasheet v1.4

ESP32-S2 Datasheet(PDF) 30 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.