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PIC16F87-I/ML Datasheet(PDF) 203 Page - Microchip Technology |
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PIC16F87-I/ML Datasheet(HTML) 203 Page - Microchip Technology |
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203 / 214 page  2003 Microchip Technology Inc. Preliminary DS30487B-page 201 PIC16F87/88 INDEX A A/D Acquisition Requirements ........................................ 117 ADIF Bit .................................................................... 116 Analog-to-Digital Converter ...................................... 113 Associated Registers ............................................... 120 Calculating Acquisition Time .................................... 117 Configuring Analog Port Pins ................................... 118 Configuring the Interrupt .......................................... 116 Configuring the Module ............................................ 116 Conversion Clock ..................................................... 118 Conversions ............................................................. 119 Converter Characteristics ........................................ 188 Delays ...................................................................... 117 Effects of a RESET .................................................. 120 GO/DONE Bit ........................................................... 116 Internal Sampling Switch (Rss) Impedance ............. 117 Operation During SLEEP ......................................... 120 Result Registers ....................................................... 119 Source Impedance ................................................... 117 Time Delays ............................................................. 117 Using the CCP Trigger ............................................. 120 Absolute Maximum Ratings ............................................. 163 ACK .................................................................................... 93 ADCON0 Register ...................................................... 14, 113 ADCON1 Register ...................................................... 15, 113 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See USART. ADRESH Register ...................................................... 14, 113 ADRESH, ADRESL Register Pair .................................... 116 ADRESL Register ...................................................... 15, 113 ANSEL Register ..............................................15, 52, 58, 113 Application Notes AN556 (Implementing a Table Read) ........................ 25 AN578 (Use of the SSP Module in the I2C Multi-Master Environment) ........................... 87 AN607 (Power-up Trouble Shooting) ....................... 133 Assembler MPASM Assembler .................................................. 157 Asynchronous Reception Associated Registers ....................................... 105, 107 Asynchronous Transmission Associated Registers ............................................... 103 B Baud Rate Generator Associated Registers ................................................. 99 BF Bit ................................................................................. 92 Block Diagrams A/D ........................................................................... 116 Analog Input Model .......................................... 117, 125 Capture Mode Operation ........................................... 82 Comparator I/O Operating Modes ............................ 122 Comparator Output .................................................. 124 Comparator Voltage Reference ............................... 128 Compare Mode Operation ......................................... 83 Fail-Safe Clock Monitor ............................................ 144 In-Circuit Serial Programming Connection ............... 147 Interrupt Logic .......................................................... 139 On-Chip Reset Circuit .............................................. 132 PIC16F87 ..................................................................... 6 PIC16F88 ..................................................................... 7 PWM .......................................................................... 84 RA0/AN0:RA1/AN1 Pins ............................................ 52 RA2/AN2/CVREF/VREF- Pin ....................................... 53 RA3/AN3/VREF+/C1OUT Pin ..................................... 53 RA4/T0CKI/C2OUT Pin ............................................. 54 RA5/MCLR/VPP Pin ................................................... 54 RA6/OSC2/CLKO Pin ................................................ 55 RA7/OSC1/CLKI Pin .................................................. 56 RB0 Pin ..................................................................... 59 RB1 Pin ..................................................................... 60 RB2 Pin ..................................................................... 61 RB3 Pin ..................................................................... 62 RB4 Pin ..................................................................... 63 RB5 Pin ..................................................................... 64 RB6 Pin ..................................................................... 65 RB7 Pin ..................................................................... 66 Recommended MCLR Circuit .................................. 133 SSP in I2C Mode ........................................................ 92 SSP in SPI Mode ....................................................... 90 System Clock ............................................................. 41 Timer0/WDT Prescaler .............................................. 67 Timer1 ....................................................................... 73 Timer2 ....................................................................... 79 USART Receive ................................................104, 106 USART Transmit ...................................................... 102 Watchdog Timer (WDT) ........................................... 141 BOR. See Brown-out Reset. BRGH bit ............................................................................ 99 Brown-out Reset (BOR) ............................ 129, 132, 133, 135 BOR Status (BOR Bit) ............................................... 24 C C Compilers MPLAB C17 ............................................................. 158 MPLAB C18 ............................................................. 158 MPLAB C30 ............................................................. 158 Capture/Compare/PWM (CCP) ......................................... 81 Capture Mode ............................................................ 82 Capture, Compare and Timer1 Associated Registers ......................................... 83 CCP Pin Configuration ............................................... 83 CCP Prescaler ........................................................... 82 CCP Timer Resources ............................................... 81 CCP1IF ...................................................................... 82 CCPR1 ...................................................................... 82 CCPR1H:CCPR1L ..................................................... 82 Compare Mode .......................................................... 83 Special Event Trigger ........................................ 83 Special Trigger Output of CCP1 ........................ 83 PWM and Timer2 Associated Registers .................... 85 PWM Mode ................................................................ 84 PWM, Example Frequencies/Resolutions ................. 85 Software Interrupt Mode ............................................ 83 Timer1 Mode Selection .............................................. 83 CCP1CON Register ........................................................... 14 CCP1M0 Bit ....................................................................... 81 CCP1M1 Bit ....................................................................... 81 CCP1M2 Bit ....................................................................... 81 CCP1M3 Bit ....................................................................... 81 CCP1X Bit .......................................................................... 81 CCP1Y Bit .......................................................................... 81 CCPR1H Register .........................................................14, 81 |
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