PIC16F87-ISLASHML datasheet(146/214 Pages) MICROCHIP

146 / 214 page

PIC16F87/88

DS30487B-page 144

Preliminary

 2003 Microchip Technology Inc.

15.12.4

FAIL-SAFE OPTION

The Fail-Safe Clock Monitor (FSCM) is designed to

allow the device to continue to operate even in the

event of an oscillator failure.

FIGURE 15-10:

FSCM BLOCK DIAGRAM

The FSCM function is enabled by setting the FCMEN

bit in Configuration Word 2.

In the event of an oscillator failure, the FSCM will gen-

erate an oscillator fail interrupt and will switch the sys-

tem clock over to the internal oscillator. The system

will continue to come from the internal oscillator until

the fail-safe condition is exited. The fail-safe condition

is exited with either a RESET, the execution of a

SLEEP

instruction or a write to the OSCCON register.

The frequency of the internal oscillator will depend

upon the value contained in the IRCF bits. Another

clock source can be selected via the IRCF and the

SCS bits of the OSCCON register.

The FSCM sample clock is generated by dividing the

INTRC clock by 64. This will allow enough time

between FSCM sample clocks for a system clock edge

to occur.

On the rising edge of the postscaled clock, the moni-

toring latch (CM = 0) will be cleared. On a falling edge

of the primary or secondary system clock, the monitor-

ing latch will be set (CM = 1). In the event that a falling

edge of the postscaled clock occurs, and the

monitoring latch is not set, a clock failure has been

detected.

While in Fail-Safe mode, a RESET will exit the fail-

safe condition. If the primary clock source is config-

ured for a crystal, the OST timer will wait for the 1024

clock cycles for the OST time-out, and the device will

continue running from the internal oscillator until the

OST is complete. A SLEEP instruction, or a write to the

SCS bits (where SCS bits do not = 00), can be

performed to put the device into a low-power mode.

If RESET occurs while in Fail-Safe mode and the pri-

mary clock source is EC, or RC, then the device will

immediately switch back to EC or RC mode.

15.12.4.1

Fail-Safe in Low-power Mode

A write to the OSCCON register, or SLEEP instruction

will end the fail-safe condition. The system clock will

default to the source selected by the SCS bits, which

is either T1OSC, INTRC, or none (SLEEP mode).

However, the FSCM will continue to monitor the sys-

tem clock. If the secondary clock fails, the device will

immediately switch to the internal oscillator clock. If

OSFIE is set, an interrupt will be generated.

FIGURE 15-11:

FSCM TIMING DIAGRAM

Peripheral

INTRC

÷ 64

31.25 kHz

(32

µs)

488 Hz

(2.048 ms)

Clock Monitor

Latch (CM)

(edge-triggered)

Clock

Failure

Detected

Oscillator

Clock

Note:

Two-Speed Start-up mode is automatically

enabled when the fail-safe option is

enabled.

OSCFIF

CM Output

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

CM Test

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