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PIC16F87-I/ML Datasheet(PDF) 189 Page - Microchip Technology |
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PIC16F87-I/ML Datasheet(HTML) 189 Page - Microchip Technology |
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189 / 214 page ![]() 2003 Microchip Technology Inc. Preliminary DS30487B-page 187 PIC16F87/88 FIGURE 18-16: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TABLE 18-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS FIGURE 18-17: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TABLE 18-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid PIC16F87/88 — — 80 ns PIC16LF87/88 — — 100 ns 121 Tckrf Clock out rise time and fall time (Master mode) PIC16F87/88 — — 45 ns PIC16LF87/88 — — 50 ns 122 Tdtrf Data out rise time and fall time PIC16F87/88 — — 45 ns PIC16LF87/88 — — 50 ns † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. Param No. Sym Characteristic Min Typ† Max Units Conditions 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK ↓ (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Refer to Figure 18-3 for load conditions. 121 121 122 RB5/TX/CK RB2/RX/DT pin pin 120 Note: Refer to Figure 18-3 for load conditions. 125 126 RB5/TX/CK RB2/RX/DT pin pin |
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