LED8102S datasheet(11/20 Pages) STMICROELECTRONICS

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Typical application

Figure 8. Typical application circuit

Typical application circuit

The figure above shows a typical application schematic for ALED8102S, Cled value depends on common rail

voltage connection length and driver total output current, typically it is around 47 µF; Cin is about 1 µF; current

setting resistor depends on outputs current set (ex. with REXT = 386 Ω → IO ≈ 50 mA). The external programming

resistor between R-EXT and GND should be connected as close as possible to the device.

To have proper device functionality it is strongly suggested to follow a correct power-up sequence: VDD and VLED

power supplies must be provided simultaneously or at least, VDD must be connected before VLED to activate all

internal digital control blocks earlier than LEDs power supply. If VLED anticipates driver VDD, this could result in a

visible flash on connected LEDs (output stage undesired activation).

Device thermal management

The aim of this section is just to provide some recommendation that can be useful in designing the application

PCB for a better power dissipation:

•

To decrease the device working temperature it is necessary solder the package exposed pad to the board.

•

For better thermal performances at least a 4 layers (e.g. 2S2P) PCB should be used.

•

The copper area below the package thermal pad should be enlarged as much as possible also outside the

package perimeter (using the package sides without pins)

•

A reasonable number of vias must connect the copper area below the package to all available PCB layers

especially just below the device package (e.g. 3x3 or 4x3 vias array) but also outside package perimeter.

Smaller and closely spaced vias is a good solution. Best implementation is represented by copper filled vias.

•

On each inner layers a copper area must be provided for dissipation (wider it's better, if possible at least

4 times or more the package dimensions). A good condition is to have at least a power layer as an entire

copper area (e.g. GND layer)

•

Traces for pins connection must be enlarged as much as layout constrains allow

•

Several devices in power dissipation on the same board must be adequately spaced.

Figure 3 shows, once the maximum power dissipation is fixed, which ambient temperature range can be covered

according to maximum junction temperature and package thermal resistance: 37.5 °C/W for HTSSOP16 on Jedec

PCB (2S2P) and conditions. With same thermal resistance, figure 4 shows the junction temperature as a function

of ambient temperature considering 1 W of power dissipation.

LED8102S

Typical application

DS12963 - Rev 3

page 11/20

LED8102S Datasheet(PDF) 11 Page - STMicroelectronics