SCH5627P datasheet(72/234 Pages) MICROCHIP

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SCH5627P

DS00001996A-page 72

 2009 - 2015 Microchip Technology Inc.

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Iden-

tification Register (refer to Table 9-11). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indi-

cates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new

interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.

IPEND

This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending.

When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate

internal service routine. When bit 0 is a logic “1”, no interrupt is pending.

IntID

These three bits of the IIR are used to identify the highest priority interrupt pending as indicated by Table 9-11. In non-

FIFO mode, Bit[3] is a logic “0”. In FIFO mode Bit[3] is set along with Bit[2] when a timeout interrupt is pending.

FIFO_En

These two bits are set when the FIFO CONTROL Register bit 0 equals 1.

TABLE 9-11:

INTERRUPT CONTROL TABLE

FIFO

Mode

Only

Interrupt Identification

Interrupt Set and Reset Functions

Bit 3

Bit 2

Bit 1

Bit 0

Priority

Level

Interrupt Type

Interrupt Source

Interrupt Reset

Control

None

Highest

Receiver Line

Status

Overrun Error,

Parity Error,

Framing Error or

Break Interrupt

Reading the Line

Status Register

Second

Received Data

Available

Receiver Data

Available

Read Receiver

Buffer or the FIFO

drops below the

trigger level.

Character Timeout

Indication

No Characters

Have Been

Removed From or

Input to the RCVR

FIFO during the

last 4 Char times

and there is at least

1 char in it during

this time

Reading the

Receiver Buffer

Third

Transmitter Holding

Reading the IIR

of Interrupt) or

Writing the

Transmitter Holding

Fourth

MODEM Status

Clear to Send or

Data Set Ready or

Ring Indicator or

Data Carrier Detect

Reading the

MODEM Status

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