6.3

T1 timer expiration: fault mode

Figure 8. T1 expiration, fault mode shows an example of platform failure triggering the protection function of the

IC. In this case, the power control unit keeps generating the power PWM signal for a time longer than expected.

As per previous case, the device exits idle mode, starts T1, turns on the internal N-channel power MOSFET and

activates the GDRV output as soon as a rising edge on PWM is detected (a).

The PWM signal keeps commutating for more than the maximum programmed on-time causing T1 to expire and

making the device enter fault mode (b).

In fault mode, the internal power MOSFET is turned off, the GDRV output is deactivated, a reset pulse on the

RESET/FAULT pin is generated and the device starts waiting for the fault condition to be removed. The condition

to exit fault mode is a low voltage level at the PWM pin for more than T2 ((d) to (e), 285 ms typ.). When the fault

removal is detected (e), T3 timer is started. During T3 (cooling window), any activity on the PWM line is ignored

and the power MOSFETs (both internal or external if used) are kept off to let the application cool down.

After T3 expires, the device enters again idle mode and is ready for a new cycle.

PWM: 30%up to 100% duty cycle

T1

T2

(b)

T3

(a)

(e)

(c) (d)

SF

OFF

SW FAULT

EXAMPLE

GDRV Status

SF ON

IC

IDLE MODE

57ms

Reset

285ms

(f)

a) Global reset on first PWM rising edge, T1 starts, SF ON

b) T1 expires, SF is turned OFF and 57 ms reset pulse is generated

c) 57 ms reset pulse ends

d) PWM stops toggling (or goes stable low) and T2 starts 285 ms timer

e) T2 expires and T3 starts

f) T3 expires, the device goes to idle mode and SF can be turned ON again if needed (by PWM rising edge)

STEC01

T1 timer expiration: fault mode

DS13063 - Rev 2

page 10/22