A111 Pulsed Coherent Radar (PCR)

Datasheet, v2.8

© 2022 Copyright by Acconeer

2022-06-22

Page 6 of 35

3.1 Functional Block Diagram

A111 One Package Solution

A111 Silicon

TX

RX

PLL

LDOs

PoR

Program

memory

Data

memory

SPI (4)

INTERRUPT

XIN (ref clk)

XOUT

1.8V Single

power supply

ENABLE

Digital

Power

Timing

mmWave Radio

Tx ant.

Rx an t.

CTRL (optional)

Figure 3.1 The A111 functional block diagram.

The A111 silicon is divided into four functional blocks: Power, Digital, Timing and mmWave radio.

The Power functional block includes LDOs and a Power on Reset (PoR) block. Each LDO creates its

own voltage domain. The PoR block generates a Reset signal on each power-up cycle. The host

interfaces the Power functional block of the sensor via 1.8 V Single power supply and ENABLE.

The Digital functional block includes sensor control. The data memory stores the radar sweep data

from the ADC. The host interfaces the Sensor via an SPI interface, a Clock (XIN, XOUT),

INTERRUPT signal and optional CTRL signal.

The Timing block includes the timing circuitry. The PLL digital clock output is used to drive digital

logic and is synthesized from external crystal (XIN/XOUT) . The operational oscillator (XIN)

frequency is 24MHz..

The mmWave radio functional block generates and receives radar pulses and includes transmitter

(TX), receiver (RX) and interfaces toward the integrated antennas. The A111 operates in the 57-64

GHz band.