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STGIPL14K60-S Datasheet(PDF) 14 Page - STMicroelectronics |
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STGIPL14K60-S Datasheet(HTML) 14 Page - STMicroelectronics |
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14 / 26 page ![]() Electrical characteristics STGIPL14K60, STGIPL14K60-S 14/26 DocID15589 Rev 11 3.2 Waveforms definitions Figure 9. Dead time and interlocking waveforms definitions LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG DTLH DTHL DTLH DTHL DTLH DTHL DTLH DTHL gate driver outputs OFF (HALF-BRIDGE TRI-STATE) CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) |
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