STM32H745II datasheet(159/252 Pages) STMICROELECTRONICS

159 / 252 page

DS12923 Rev 1

159/252

STM32H745xI/G

Electrical characteristics

228

6.3.17

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 69: I/O static characteristics).

Unless otherwise specified, the parameters given in Table 74 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 23: General operating conditions.

Figure 26. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 69. Otherwise the reset is not taken into account by the device.

6.3.18

FMC characteristics

Unless otherwise specified, the parameters given in Table 75 to Table 88 for the FMC

interface are derived from tests performed under the ambient temperature, fHCLK frequency

and VDD supply voltage conditions summarized in Table 23: General operating conditions,

with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Measurement points are done at CMOS levels: 0.5VDD

•

IO Compensation cell activated.

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS1.

Table 74. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RPU(2)

Weak pull-up equivalent

resistor(1)

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum

(~10% order)

VIN = VSS

㏀

VF(NRST)(2)

2. Guaranteed by design.

NRST Input filtered pulse

1.71 V < VDD < 3.6 V

VNF(NRST)(2) NRST Input not filtered pulse

1.71 V < VDD < 3.6 V

300

1.62 V < VDD < 3.6 V

1000

ai14132d

STM32

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 μF

External

reset circuit (1)

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