STM32L062C8 datasheet(83/124 Pages) STMICROELECTRONICS

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DS10183 Rev 11

83/124

STM32L062x8

Electrical characteristics

101

RAIN(3)

External input impedance

See Equation 1 and

Table 56 for details

RADC(3)(4)

Sampling switch resistance

CADC(3)

Internal sample and hold

capacitor

tCAL(3)(5)

Calibration time

fADC = 16 MHz

5.2

µs

-83

1/fADC

WLATENCY(6)

ADC_DR register write

latency

ADC clock = HSI16

1.5 ADC

cycles + 2

fPCLK cycles

1.5 ADC

cycles + 3

fPCLK cycles

ADC clock = PCLK/2

4.5

fPCLK

cycle

ADC clock = PCLK/4

8.5

fPCLK

cycle

tlatr(3)

Trigger conversion latency

fADC = fPCLK/2 = 16 MHz

0.266

µs

fADC = fPCLK/2

8.5

1/fPCLK

fADC = fPCLK/4 = 8 MHz

0.516

µs

fADC = fPCLK/4

16.5

1/fPCLK

fADC = fHSI16 = 16 MHz

0.252

0.260

µs

JitterADC

ADC jitter on trigger

conversion

fADC = fHSI16

-1

1/fHSI16

tS(3)

Sampling time

fADC = 16 MHz

0.093

10.03

µs

-1.5

160.5

1/fADC

tUP_LDO(3)(5) Internal LDO power-up time

µs

tSTAB(3)(5)

ADC stabilization time

1/fADC

tConV(3)

Total conversion time

(including sampling time)

fADC = 16 MHz,

12-bit resolution

0.875

10.81

µs

12-bit resolution

14 to 173 (tS for sampling +12.5

for successive approximation)

1/fADC

1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 56: RAIN max for fADC = 16 MHz.

2. A current consumption proportional to the APB clock frequency has to be added (see Table 33: Peripheral current

consumption in Run or Sleep mode).

3. Guaranteed by design.

4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 56: RAIN max for

fADC = 16 MHz.

5. This parameter only includes the ADC timing. It does not take into account register access latency.

6. This parameter specifies the latency to transfer the conversion result into the ADC_DR register. EOC bit is set to indicate the

conversion is complete and has the same latency.

Table 55. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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