STM32L062C8 datasheet(26/124 Pages) STMICROELECTRONICS

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Functional overview

STM32L062x8

26/124

DS10183 Rev 11

3.8

Memories

The STM32L062x8 devices have the following features:

•

8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states. With the enhanced bus matrix, operating the RAM does not lead to any

performance penalty during accesses to the system bus (AHB and APB buses).

•

The non-volatile memory is divided into three arrays:

–

32 or 64 Kbytes of embedded Flash program memory

–

2 Kbytes of data EEPROM

–

Information block containing 32 user and factory options bytes plus 4 Kbytes of

system memory

The user options bytes are used to write-protect or read-out protect the memory (with

4 Kbyte granularity) and/or readout-protect the whole memory with the following options:

•

Level 0: no protection

•

Level 1: memory readout protected.

The Flash memory cannot be read from or written to if either debug features are

connected or boot in RAM is selected

•

Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in

RAM selection disabled (debugline fuse)

The firewall protects parts of code/data from access by the rest of the code that is executed

outside of the protected area. The granularity of the protected code segment or the non-

volatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the

volatile data segment (RAM).

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.9

Boot modes

At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:

•

Boot from Flash memory

•

Boot from System memory

•

Boot from embedded RAM

The boot loader is located in System memory. It is used to reprogram the Flash memory by

using SPI1(PA4, PA5, PA6, PA7), USART1(PA9, PA10) or USART2(PA2, PA3). See

STM32 microcontroller system memory boot mode AN2606 for details.

STM32L062C8 Datasheet(PDF) 26 Page - STMicroelectronics

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