MPC8540 datasheet(253/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-3

6.2

Embedded 32-bit processors implement the following types of software-accessible registers:

•

Book E–defined registers that are accessed as part of instruction execution. These include

the following:

— Registers used for computation. These include the following:

– General-purpose registers (GPRs)—Book E defines a set of 32 GPRs used to hold

source and destination operands for load, store, arithmetic, and computational

instructions, and to read and write to other registers. The e500 implements these as

64-bit registers for use with 64-bit load, store, and merge instructions, as described

in Section 6.3.1, “General-Purpose Registers (GPRs).”

– Integer exception register (XER)—Bits in this register are set based on the operation

of an instruction considered as a whole, not on intermediate results. (For example,

the Subtract from Carrying instruction (subfc), the result of which is specified as the

sum of three values, sets bits in the XER based on the entire operation, not on an

intermediate sum.)

These registers are described in Section 6.3, “Registers for Computational Operations.”

— Condition register (CR)—Used to record conditions such as overflows and carries that

occur as a result of executing arithmetic instructions (including those implemented by

the SPE APU). The CR is described in Section 6.4, “Registers for Branch Operations.”

— Machine state register (MSR)—Used by the operating system to configure parameters

such as user/supervisor mode, address space, and enabling of asynchronous interrupts.

This register is described in Section 6.5.1, “Machine State Register (MSR),” grouped

with processor control SPRs.

•

Book E–defined special-purpose registers (SPRs) that are accessed explicitly using mtspr

and mfspr instructions. These registers are listed in Table 6-1 in Section 6.2.1,

“Special-Purpose Registers (SPRs).”

•

Freescale Semiconductor EIS– and e500-defined SPRs that are accessed explicitly using

mtspr and mfspr are listed in Table 6-2 in Section 6.2.1, “Special-Purpose Registers

(SPRs).”

•

Freescale Semiconductor EIS–defined performance monitor registers (PMRs). These

registers are similar to SPRs, but are accessed with Freescale Semiconductor EIS–defined

move to and move from PMR instructions (mtpmr and mfpmr).

In this chapter, SPRs are grouped by function as follows:

•

Section 6.4, “Registers for Branch Operations,” describes the count register (CTR) and the

link register (LR) defined by Book E.

•

Section 6.5, “Processor Control Registers”

•

Section 6.6, “Timer Registers”

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