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MPC8540 Datasheet(PDF) 256 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 256 Page - Freescale Semiconductor, Inc |
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256 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 6-6 Freescale Semiconductor Core Register Summary Table 6-2 describes the implementation-specific SPRs. Compilers should recognize the mnemonic names given in Table 6-2 when parsing instructions. SPRG5 SPR general 5 261 01000 00101 Read-only No 6.8/6-24 277 01000 10101 Read/Write Yes SPRG6 SPR general 6 262 01000 00110 Read-only No 278 01000 10110 Read/Write Yes SPRG7 SPR general 7 263 01000 00111 Read-only No 279 01000 10111 Read/Write Yes SRR0 Save/restore register 0 26 00000 11010 Read/Write Yes 6.7.1.1/6-18 SRR1 Save/restore register 1 27 00000 11011 Read/Write Yes 6.7.1.2/6-18 TBL Time base lower 268 01000 01100 Read-only No 6.6.3/6-17 284 01000 11100 Write-only Yes TBU Time base upper 269 01000 01101 Read-only No 285 01000 11101 Write-only Yes TCR Timer control register 340 01010 10100 Read/Write Yes 6.6.1/6-15 TSR Timer status register 336 01010 10000 Read/Clear4 Yes 6.6.2/6-16 USPRG0 User SPR general 05 256 01000 00000 Read/Write No 6.8/6-24 XER Integer exception register 1 00000 00001 Read/Write No 6.3.2/6-8 1 The DBSR is read using mfspr. It cannot be directly written to. Instead, DBSR bits corresponding to 1 bits in the GPR can be cleared using mtspr. 2 Implementations may support more than one PID. For implementations with multiple PIDs, the EIS implements the Book E–defined PID as PID0. 3 User-mode read access to SPRG3 is implementation dependent. 4 The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in the GPR can be cleared using mtspr. 5 USPRG0 is a separate physical register from SPRG0. Table 6-2. Implementation-Specific SPRs (by SPR Abbreviation) SPR Abbreviatio n Name SPR Number Access Superviso r Only Section/ Page BBEAR Branch buffer entry address register 513 Read/Write No 6.9.1/6-25 BBTAR Branch buffer target address register 514 Read/Write No 6.9.2/6-25 BUCSR Branch unit control and status register 1013 Read/Write Yes 6.9.3/6-26 HID0 Hardware implementation dependent reg 0 1008 Read/Write Yes 6.10.1/6-27 HID1 Hardware implementation dependent reg 1 1009 Read/Write Yes 6.10.1/6-27 Table 6-1. Book E Special-Purpose Registers (by SPR Abbreviation) (continued) SPR Abbreviatio n Name Defined SPR Number Access Superviso r Only Section/ Page Decimal Binary |
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