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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-8

Freescale Semiconductor

Core Register Summary

6.3

Registers for Computational Operations

The following sections describe general-purpose and integer exception registers.

NOTE

writing ones to them. Writing zeros to them has no effect.

6.3.1

General-Purpose Registers (GPRs)

Book E implementations provide 32 GPRs (GPR0–GPR31) for integer operations. The instruction

formats provide 5-bit fields for specifying the GPRs to be used in the execution of the instruction.

Each GPR is a 64-bit register, although only 64-bit load, store, and merge instructions use GPR

bits 0–31.

6.3.2

Integer Exception Register (XER)

TLB0CFG

TLB configuration register 0

688

Read-only

Yes

6.12.4/6-35

TLB1CFG

TLB configuration register 1

689

Read-only

Yes

6.12.4.2/6-3

56 57

Field

—

Number of bytes

Reset

All zeros

R/W

SPR

SPR 1

Figure 6-2. Integer Exception Register (XER)

Table 6-2. Implementation-Specific SPRs (by SPR Abbreviation) (continued)

SPR

Abbreviatio

Name

SPR Number

Access

Superviso

Only

Section/

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