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MPC8540 Datasheet(PDF) 261 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 261 Page - Freescale Semiconductor, Inc |
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261 / 1302 page ![]() Processor Control Registers MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 6-11 The bits of CR0 are interpreted as described in Table 6-5. 6.4.2 Link Register (LR) 6.4.3 Count Register (CTR) 6.5 Processor Control Registers This section addresses machine state, processor ID, and processor version registers. Table 6-5. CR0 Bit Descriptions CR Bit Name Description 32 Negative (LT) Bit 32 of the result is equal to 1. 33 Positive (GT) Bit 32 of the result is equal to 0 and at least one bit from 33–63 of the result is non-zero. 34 Zero (EQ) Bits 32–63 of the result are equal to 0. 35 Summary overflow (SO) This is a copy of the final state of XER[SO] at the completion of the instruction. 32 63 Field Link address Reset All zeros R/W R/W SPR SPR 8 Figure 6-4. Link Register (LR) 32 63 Field Count value Reset All zeros R/W R/W SPR SPR 9 Figure 6-5. Count Register (CTR) |
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