MPC8540 datasheet(265/1302 Pages) FREESCALE

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Timer Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-15

6.6

Timer Registers

6.6.1

Timer Control Register (TCR)

32 33 34 35

38 39

42 43

46 47

50 51

Field WP WRC WIE DIE

FIE ARE —

WPEXT

FPEXT

—

Reset

All zeros

R/W

SPR

SPR 340

Figure 6-10. Timer Control Register (TCR)

Table 6-8. TCR Field Descriptions

Bits

Name

Description

32–33

Watchdog timer period. When concatenated with WPEXT, specifies one of 64-bit locations of the time base

used to signal a watchdog timer exception on a transition from 0 to 1.

WPEXT[0–3] || WP[0–1] = 0b00_0000 selects TBU[32] (the msb of the TB)

WPEXT[0–3] || WP[0–1] = 0b11_1111 selects TBL[63] (the lsb of the TB)

34–35

WRC

Watchdog timer reset control. This value is written into TSR[WRS] when a watchdog event occurs. WRC may

be set by software but cannot be cleared by software, except by a software-induced reset. Once written to a

non-zero value, WRC may no longer be altered by software.

00 No watchdog timer reset will occur.

01 A second timeout is ignored, regardless of the value of MSR[ME].

10 Assert processor reset output (core_hreset_req) on second timeout of watchdog timer

11 Reserved

WIE

Watchdog timer interrupt enable

0 Watchdog timer interrupts disabled

1 Watchdog timer interrupts enabled

DIE

Decrementer interrupt enable

0 Decrementer interrupts disabled

1 Decrementer interrupts enabled

38–39

Fixed interval timer period. When concatenated with FPEXT, FP specifies one of 64 bit locations of the time

base used to signal a fixed-interval timer exception on a transition from 0 to 1.

FPEXT[0–3] || FP[0–1] = 0b00_0000 selects TBU[32] (the msb of the TB)

FPEXT[0–3] || FP[0–1] = 0b11_1111 selects TBL[63] (the lsb of the TB)

FIE

Fixed interval interrupt enable

0 Fixed interval interrupts disabled

1 Fixed interval interrupts enabled

ARE

Auto-reload enable. Controls whether the DECAR value is reloaded into the DEC when the DEC value reaches

0000_0001. See EREF: A Reference for Freescale Semiconductor Book E and the e500 Core.

0 Auto-reload disabled

1 Auto-reload enabled

—

Reserved, should be cleared.

43–46 WPEXT Watchdog timer period extension (see the description for WP)

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