MPC8540 datasheet(266/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-16

Freescale Semiconductor

Core Register Summary

6.6.2

Timer Status Register (TSR)

47–50

FPEXT

Fixed-interval timer period extension (see the description for FP)

51–63

—

Reserved, should be cleared.

Field ENW WIS

WRS

DIS

FIS

—

Reset

All zeros

R/W Set by hardware. Read with mfspr and cleared with mtspr by writing ones to any TSR bit positions to be cleared

and zeros in all other bit positions.

SPR

SPR 336

Figure 6-11. Timer Status Register (TSR)

Table 6-9. TSR Field Descriptions

Bits

Name

Description

ENW Enable next watchdog time. Functions as write-one-to-clear.

0 Action on next watchdog timer time-out is to set TSR[ENW]

1 Action on next watchdog timer time-out is governed by TSR[WIS]

When a watchdog timer time-out occurs while WIS = 0 and the next watchdog time-out is enabled

(ENW = 1), a watchdog timer exception is generated and logged by setting WIS. This is referred to as

a watchdog timer first time out. A watchdog timer interrupt occurs if enabled by TCR[WIE] and

MSR[CE]. To avoid another watchdog timer interrupt once MSR[CE] is reenabled, (assuming

TCR[WIE] is not cleared instead), the interrupt handler must reset TSR[WIS].

WIS

Watchdog timer interrupt status. Functions as write-one-to-clear.

0 A watchdog timer event has not occurred.

1 A watchdog timer event occurred. When MSR[CE] = 1 and TCR[WIE] = 1, a watchdog timer

interrupt is taken.

See the description of ENW for more information about how WIS is used.

34–35

WRS

Watchdog timer reset status. Functions as write-one-to-clear. Defined at reset (value = 00). Set to

TCR[WRC] when a reset is caused by the watchdog timer.

DIS

Decrementer interrupt status. Functions as write-one-to-clear.

0 A decrementer event has not occurred.

1 A decrementer event occurred. When MSR[EE] = TCR[DIE] = 1, a decrementer interrupt is taken.

FIS

Fixed-interval timer interrupt status. Functions as write-one-to-clear.

0 A fixed-interval timer event has not occurred.

1 A fixed-interval timer event occurred. When MSR[EE] = 1 and TCR[FIE] = 1, a fixed-interval timer

interrupt is taken.

38–63

—

Reserved, should be cleared.

Table 6-8. TCR Field Descriptions (continued)

Bits

Name

Description

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