MPC8540 datasheet(262/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-12

Freescale Semiconductor

Core Register Summary

6.5.1

Machine State Register (MSR)

57 58

62 63

Field

—

UCLE SPE

—

WE CE — EE PR — ME

—

UBLE DE

—

IS DS — PMM

—

Reset

All zeros

R/W

Figure 6-6. Machine State Register (MSR)

Table 6-6. MSR Field Descriptions

Bits

Name

Description

32–36

—

Reserved, should be cleared.1

UCLE User-mode cache lock enable (defined by the EIS). Used to restrict user-mode cache-line locking by

the operating system

0 Any cache lock instruction executed in user-mode takes a cache-locking DSI exception and sets

either ESR[DLK] or ESR[ILK]. This allows the operating system to manage and track the

locking/unlocking of cache lines by user-mode tasks.

1 Cache-locking instructions can be executed in user-mode and they do not take a DSI for

cache-locking (they may still take a DSI for access violations though).

SPE

SPE enable (defined by the EIS)

0 If software attempts to execute an SPE APU or SPFP instruction, an SPE APU unavailable

exception is taken.

1 Software can execute supported SPE and SPFP APU instructions.

Note: The SPE APU and SPFP APU functionality will be implemented in the all PowerQUICC III

devices. However, these instructions will not be supported in devices subsequent to PowerQUICC III.

Freescale Semiconductor strongly recommends that use of these instructions be confined to libraries

and device drivers. Customer software that uses SPE or SPFP APU instructions at the assembly level

or that uses SPE intrinsics will require rewriting for upward compatibility with next generation

PowerQUICC devices.

Freescale Semiconductor offers a libmoto_e500 library that uses SPE and SPFP APU instructions.

Freescale will also provide future libraries to support next-generation PowerQUICC devices.

39–44

—

Reserved, should be cleared. 1

Wait state enable. Allows the core complex to signal a request for power management, according to

the states of HID0[DOZE], HID0[NAP], and HID0[SLEEP].

0 The processor is not in wait state and continues processing. No power management request is

signaled to external logic.

1 The processor enters wait state by ceasing to execute instructions and entering low-power mode.

Details of how wait state is entered and exited and how the processor behaves in the wait state are

implementation-dependent. On the e500, MSR[WE] gates the DOZE, NAP, and SLEEP outputs

from the core complex; as a result, these outputs negate to the external power management logic

on entry to the interrupt and then return to their previous state on return from the interrupt. WE is

cleared on entry to any interrupt and restored to its previous state upon return.

Critical enable

0 Critical input and watchdog timer interrupts are disabled.

1 Critical input and watchdog timer interrupts are enabled.

—

Preserved for Book III ILE

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